1. Field of the Invention
The present invention relates to a voltage comparator circuit, and in particular, relates to a voltage comparator circuit suitable for a high-speed differential signal interface.
2. Description of the Related Art
Differential signaling is one of the well-known approaches for achieving a high-speed signal interface. For example, RSDS™ (Reduced Swing Differential Signaling), and mini-LVDS™ (Low Voltage Differential Signaling) are going to be standardized as an interfacing scheme between an LCD (Liquid Crystal Display) driver and a timing controller within an LCD apparatus.
Receiver circuits used for differential signaling typically incorporate a voltage comparator circuit with differential inputs. Differential signals received by a differential signal receiver typically have a frequency of approximately 85 MHz for RSDS™, and 200 MHz for mini-LVDS™. The amplitude of the differential signal component of the differential signals is approximately ±50 mV, and the amplitude of the common-mode signal component ranges from 0.3 V to VDD−0.5 V, where VDD is a power supply voltage. A voltage comparator circuit within a receiver circuit is required to meet the specifications described above. With a circuit configuration presently released, however, it is difficult to satisfy both the specifications of the common-mode signal component, and an operation speed at the same time.
A voltage comparator circuit adapted to differential signals is typically based on a differential amplifier topology. FIG. 1 is a circuit diagram illustrating a structure of a differential amplifier circuit disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 03-62712). The conventional differential amplifier circuit is provided with first and second differential transistor pairs DF11 and DF12, first to fifth current mirror circuits CM11 to CM15, and first and second constant current sources I11 and I12.
The first differential transistor pair DF11 is composed of first and second P-channel MOS transistors MP11 and MP12. Correspondingly, the second differential transistor pair DF12 is composed of first and second N-channel MOS transistors MN11 and MN12.
The first current mirror circuit CM11 has an input terminal connected to the drain of the first P-channel MOS transistor MP11, a common terminal connected to an earth terminal (VSS terminal), and an output terminal connected to the input terminal of the fifth current mirror circuit CM15. The second current mirror circuit CM12, on the other hand, has an input terminal connected to the drain of the second P-channel MOS transistor MP12, a common terminal connected to the VSS terminal, and an output terminal connected to an output terminal OUT of the differential amplifier circuit.
The third current mirror circuit CM13 has an input terminal connected to the drain of the first N-channel MOS transistor MN11, a common terminal connected to a power supply terminal (VDD terminal), and an output terminal connected to the drain of the second P-channel MOS transistor MP12 and also to the input terminal of the second current mirror circuit CM12. The fourth current mirror circuit CM14 has an input terminal connected to the drain of the second N-channel MOS transistor MN12, a common terminal connected to the VDD terminal; and the output terminal is connected to the input terminal of the first current mirror circuit CM11 and also to the drain of the first P-channel MOS transistor MP11. Finally, the fifth current mirror circuit CM15 has an input terminal connected to the output terminal of the first current mirror circuit CM11, a common terminal connected to the VDD terminal, and an output terminal connected to the output terminal of the second current mirror circuit CM12 and also to the output terminal OUT of the differential amplifier circuit.
The first constant current source I11 is connected between the VDD terminal and the commonly-connected sources of the first and second P-channel MOS transistor MP11 and MP12. The second constant current source I12 is connected between the VSS terminal and the commonly-connected sources of the first and second N-channel MOS transistors MN11 and MN12.
The gates of the first P-channel MOS transistor MP11 and the first N-channel MOS transistor MN11 are commonly connected to an inverting input terminal In− of the differential amplifier circuit. Correspondingly, the gates of the second P-channel MOS transistor MP12 and the second N-channel MOS transistor MN12 are commonly-connected to non-inverting input terminal In+.
Operation analysis the conventional differential amplifier circuit shown in FIG. 1 is given in the following.
First, basic operation of a differential transistor pair is described with reference to FIGS. 2 and 3. FIG. 2 shows a basic circuit configuration of the differential transistor pair, and FIG. 3 shows input-to-output characteristics of the differential transistor pair. The studied differential transistor pair is composed of N-channel MOS transistors MN21 and MN22 having commonly-connected sources. A constant current source ISS for supplying an electric current Iss is connected between the commonly-connected sources and a VSS terminal. When a set of DC voltages Vi1 and Vi2 are supplied to the gates of the N-channel MOS transistors MN21, and MN22, respectively, the following formula (1) holds:Vi1−VGS1+VGS2−Vi2=0  (1)where VGS1 and VGS2 are gate-source voltages of the N-channel MOS transistors MN21 and MN22, respectively.
Additionally, the gate-source voltages VGS1 and VGS2 are represented by the following formulas:
                    β        =                              W            L                    ⁢          μ          ⁢                                          ⁢                      C            O                                              (        2        )                                          V          GS1                =                                                            2                ⁢                                  I                  d1                                            β                                +                      V            T                                              (        3        )                                          V          GS2                =                                                            2                ⁢                                  I                  d2                                            β                                +                      V            T                                              (        4        )            where Id1 and Id2 are drain currents through the MOS transistors MN21 and MN22, respectively, and W and L are the gate width and length of the N-channel MOS transistors MN21 and MN22, respectively; μ is the mobility, and C0 is the gate oxide film capacitance per unit area; finally, VT is the threshold voltage of the N-channel MOS transistors MN21 and MN22.
From formulas (1) to (4), a minimum voltage difference ΔVid between the input voltages Vi1 and Vi2 at which the whole of the bias current Iss from the constant current source ISS flows only through the N-channel MOS transistor MN21 is indicated by the following formula (5):
                              Δ          ⁢                                          ⁢                      V            id                          =                                            V              i1                        -                          V              i2                                =                                                    (                                                                                                    2                        ⁢                                                  I                          SS                                                                    β                                                        +                                      V                    T                                                  )                            -                              V                T                                      =                                                            2                  ⁢                                      I                    SS                                                  β                                                                        (        5        )            
In the following, a common gate-source voltage VGS0 is defined as the gate-source voltages of the N-channel MOS transistors MN21 and MN22 for Vi1=Vi2. Since the drain currents Id1 and Id2 through the N-channel MOS transistors MN21 and MN22 are each identical to half of the bias current Iss, the common gate-source voltage VGS0 is represented by the following formula (6):
                              V          GS0                =                                                            I                SS                            β                                +                      V            T                                              (        6        )            
From formulas (5) and (6), the minimum voltage difference ΔVid at which the differential transistor pair appropriately operates is represented as follows:∴ΔVid=√{square root over (2)}(VGS0−VT)  (7)
Formula (7) presents the condition under which the bias current flows through only one MOS transistor within the differential transistor pair.
Thus, the bias current flows through only one transistor, not through the other transistor within the differential transistor pair, when the input voltage difference is equal to or more than the value defined by formula (7). This operation is the basic principle of comparator operation. The differential transistor pair exhibits the input-to-output characteristics shown in FIG. 3; the horizontal axis represents the voltage difference between the input voltages Vi1 and Vi2, and the vertical axis represents the drain currents through the N-channel MOS transistors MN21 and MN22.
It should be noted that the comparator operation may be sufficiently achieved when the voltage difference is equal to or below the value defined by formula (7), depending on a configuration of a next circuit stage connected to the differential transistor pair; this is because the differential transistor pair has a sufficient gain.
Next, the conventional differential amplifier circuit in FIG. 1 is then analyzed in the following. The circuit shown in FIG. 1 is responsive to the input voltage levels to operate in selected one of three operation modes: (1) an operation mode in which both the first and second differential transistor pairs DF11 and DF12 are activated, (2) an operation mode in which only the first differential transistor pair DF11 is activated; and (3) an operation mode in which only the second differential transistor pair DF12 is activated.
(1) In Case when Both of First and Second Differential Transistor Pairs DF11 and DF12 are Activated
Both of the first and second differential transistor pairs DF11 and DF12 are activated when the conditions defined by the following formula are satisfied.VDD−(VGS(MP)+VDS(sat)(I11))>Vin>VGS(MN)+VDS(sat)(I12)  (8)where Vin is any of the input voltages Vin− and Vin+ supplied to the inverting and non-inverting input terminals In− and In+, respectively; VGS(MP) is the gate-source voltage of the P-channel MOS transistors MP11 or MP12, and VGS(MN) is the gate-source voltage of the N-channel MOS transistor MN11 or MN12; VDS(sat)(I11) is a drain-source voltage at saturation of a P-channel MOS transistor (not shown) within the current source I11; and VDS(sat)(I12) is the drain-source voltage at saturation of an N-channel MOS transistor (not shown) within the current source I12. It should be noted that a drain-source voltage at saturation of a MOS transistor is a voltage barely enough for the MOS transistor to operate in a pentode region.
(1-a) Operation for Vin−>Vin+
First, a description is given for a case where the input voltage Vin− is higher than the input voltage Vin+, and the difference between the input voltages Vin− and Vin+ is larger than the voltage ΔVid, defined by formula (7). It should be noted that the input voltages Vin− and Vin+ are defined as the voltages applied to the inverting input terminals In− and In+, respectively. In this case, the differential amplifier circuit performs voltage comparator operation, and thus the bias current I1 flows only through the P-channel MOS transistor MP12 within the differential transistor pair DF11; the current through the first P-channel MOS transistor MP11 is nil. Correspondingly, the bias current I2 flows only through the N-channel MOS transistor MN11 within the differential transistor pair DF12, and the current through the N-channel MOS transistor MN12 is nil.
In this case, each current mirror circuit operates as follows. The current mirror circuit CM13 develops an output current having a level identical to that of the bias current I2, since the N-channel MOS transistor MN11 allows the bias current I2 to be drawn from the input of the current mirror circuit CM13; it should be noted that the circle attached to each of the blocks referred to as each current mirror circuit represents the input terminal. The second current mirror circuit CM12 receives an input current which is the drain current I1 of the second P-channel MOS transistor MP12 and the output current I2 of the third current mirror circuit CM13 added together. The current mirror circuit CM12 is designed to have a mirror ratio of k; that is, the current mirror circuit CM12 develops an output current having a current level of k times of that of the input current inputted thereto. Therefore, the output current IO(CM12) of the current mirror circuit CM12 is represented by the following formula:IO(CM12)=k(I1+I2)  (9)
On the other hand, the input current of the current mirror circuit CM14 is nil, since the current through the N-channel MOS transistor MN12 is nil. This results in that the output current of the current mirror circuit CM14 is set nil. Additionally, the current mirror circuit CM11 receives an input current which is the output current of the current mirror circuit CM14 and the drain current of the P-channel MOS transistor MP11 added together. The output current of the current mirror circuit CM14 and the drain current of the P-channel MOS transistor MP11 are both nil, and therefore the input current of the current mirror circuit CM11 is also nil. Accordingly, the output current of the current mirror circuit CM11 is set nil. Since the output current of the current mirror circuit CM11 is nil, the input current of the current mirror circuit CM15 is nil, and therefore the output current of the current mirror circuit CM15 is also nil.
As is understood from the foregoing, the differential amplifier circuit operates to draw a current from the output terminal OUT due to the operation of the current mirror circuit CM12. The current level IOUT on the output terminal OUT is represented by the following formula:IOUT=k(I1+I2)  (10)This results in that the voltage level on the output terminal OUT is pulled down to the low level (GND).
(1-b) Operation for Vin−<Vin+
Next, a description is given for a case where the input voltage Vin+ is higher than the input voltage Vin−, and the difference between the input voltages Vin+ and Vin− is equal to or above the value defined by Formula (7). In this case, the differential amplifier circuit performs the comparator circuit operation, and therefore the bias current I1 flows only through the P-channel MOS transistor MP11 within the differential transistor pair DF11, and the current through the P-channel MOS transistor MP12 is set nil. Correspondingly, the bias current I2 flows only through the N-channel MOS transistor MN12 within the differential transistor pair DF12, and the current through the N-channel MOS transistor MN11 is set nil.
In this case, each current mirror circuit operates as follows. The current mirror circuit CM14 develops an output current having a level identical to that of the bias current I2, since the N-channel MOS transistor MN12 allows the bias current I2 to be drawn from the input of the current mirror circuit CM14. The current mirror circuit CM11 receives an input current which is the drain current I1 of the P-channel MOS transistor MP11 and the output current I2 of the current mirror circuit CM14 added together Therefore, the output current IO(CM11) of the current mirror circuit CM11 is represented by the following formula:IO(CM11)=I1+I2  (11)
The output of the current mirror circuit CM11 is connected with the input of the current mirror circuit CM15, and therefore the input current of the current mirror circuit CM15 is (I1+I2). The current mirror circuit CM15 is designed to have a mirror ratio of k, that is, the current mirror circuit CM15 develops an output current having a current level of k times of that of the input current inputted thereto. Therefore, the output current IO(CM15) of the current mirror circuit CM15 is represented by the following formula:IO(CM15)=k(I1+I2)  (12)
On the other hand, the input current of the current mirror circuit CM13 is nil, since the drain current of the N-channel MOS transistor MN11 is set nil. Therefore, the output current of the current mirror circuit CM13 is also set nil. The current mirror circuit CM12 receives an input current which is the output current of the current mirror circuit CM13 and the drain current of the P-channel MOS transistor MP12 added together. Since these currents are both nil, the input current of the current mirror circuit CM12 is nil, and the output current thereof is also set nil.
From the foregoing, the differential amplifier circuit operates to supply a current from the output terminal OUT due to the operation of the current mirror circuit CM15. The current IOUT developed on the output terminal OUT is represented by the following formula:IOUT=k(I1+I2)  (13)This results in that the voltage level on the output terminal OUT is pulled up to the high level (VDD).
In summary, the differential amplifier circuit operates to draw or supply a current through the output terminal IOUT in response to the voltage level difference between the inverting input terminal In− and the non-inverting input terminal In+, when both the first differential transistor pairs DF11 and DF12 are activated. The current level on the output terminal OUT is represented by formulas (10) and (13).
(2) In Case where Only First Differential Transistor Pair DF11 is Activated
Only the first differential transistor pair DF11 is activated when the input voltages Vin− and Vin+ satisfy conditions defined by the following formulas:0<Vin<VGS(MN)+VDS(sat)(I12)  (14)where VGS(MN) is the gate-source voltage of the N-channel MOS transistors MN11 or MN12, and VDS(sat)(I12) is the drain-source voltage at saturation of the N-channel MOS transistor (not shown) within the current source I12.
In such input voltage range, a sufficient drain-source voltage is not established across the MOS transistor within the constant current source I12, and therefore the bias current I2 is set nil. As a result, the differential transistor pair DF12 is deactivated.
(2-a) Operation for Vin−>Vin+
First, a description is given for a case where the input voltage Vin− is higher than the input voltage Vin+, and the voltage difference between the input voltages Vin− and Vin+ are equal to or above the minimum voltage difference ΔVid defined by formula (7). Under these conditions, the bias current I1 flows only through the P-channel MOS transistor MP12 within the differential transistor pair DF11, and therefore the current through the first P-channel MOS transistor MP11 is nil. Additionally, the bias current I2 through the differential transistor pair DF12 is nil.
In this case, each current mirror circuit operates as follows: No electric current flows through the current mirror circuits CM13 and CM14, since the bias current I2 is nil. The input current of the current mirror circuit CM11 is set nil, since the output current of the current mirror circuit CM14 and the drain current of the P-channel MOS transistor MP11 are nil. Therefore, the output current of the current mirror circuit CM11, which is identical to the input current of the current mirror circuit CM15, is also set nil. Because the input current of the current mirror circuit CM15 is nil, the output current thereof is also set nil.
The current mirror circuit CM12, on the other hand, receives the drain current of the P-channel MOS transistor MP12 within the differential transistor pair DF11, while the output current of the current mirror circuit CM13 is nil. That is, the input current of the current mirror circuit CM12 is identical to the drain current I1 of the P-channel MOS transistor MP12, and therefore the current mirror circuit CM12 develops an output current having a current level of k times of that the input current. Accordingly, the differential amplifier circuit operates to draw a current from the output terminal OUT due to the operation of the current mirror circuit CM12. The current level IOUT on the output terminal OUT is equal to k·I1, and the output voltage on the output terminal OUT is pulled down to the low level (GND).
(2-b) Operation for Vin−<Vin+)
Next, a description is given for a case where the voltage Vin+ is higher than the voltage Vin−, and the voltage difference between the voltages Vin+ and Vin− is equal to or above the minimum voltage difference defined by formula (7). Under these conditions, the bias current I1 flows only through the P-channel MOS transistor MP11 within the differential transistor pair DF11, and the current through the P-channel MOS transistor MP12 is nil. Additionally, the bias current I2 of the differential transistor pair DF12 is nil.
In this case, each current mirror circuit operates as follows: No electric current flows through the current mirror circuits CM13 and CM14, since the bias current I2 of the differential transistor pair DF12 is nil. Since the output current of the current mirror circuit CM13 and the drain current of the P-channel MOS transistor MP12 are both nil, the input current of the current mirror circuit CM12 is also nil, and the output current of the current mirror circuit CM12 is set nil.
The current mirror circuit CM11, on the other hand, receives the drain current of the P-channel MOS transistor MP11 within the differential transistor pair DF11, while the output current of the current mirror circuit CM14 is nil. That is, the input current of the current mirror circuit CM11 is identical to the drain current I1 of the P-channel MOS transistor MP11, and the current mirror circuit CM11 develops an output current having a current level identical to that of the input current I1, which is to be supplied to the input of the current mirror circuit CM15.
The current mirror circuit CM15 receives the output current of the current mirror circuit CM11 on the input, and therefore develops an output current having a current level of k times of that of the input current inputted thereto. The differential amplifier circuit supplies a current from the output terminal OUT due to the operation of the current mirror circuit CM15. The current level IOUT on the output terminal OUT is equal to k·I1. This results in that the voltage level on the output terminal OUT is pulled up to the high level (VDD).
In summary, the differential amplifier circuit operates to draw or supply a current through the output terminal OUT in response to the input voltage difference between the inverting input terminal In− and the non-inverting input terminal In+. The current level on the output terminal OUT is represented by the following formula in the both cases:IOUT=kI1  (15)(3) In Case where Only the Second Differential Transistor Pair DF12 is Activated
Only the second differential transistor pair DF12 is activated in a case where the input voltages Vin− and Vin+ satisfy conditions defined by the following formulas:VDD>Vin>VDD−(VGS(MP)+VDS(sat)(I11))  (16)where VGS(MP) is the gate-source voltage of the P-channel MOS transistors MP11 or MP12, and VDS(sat)(I11) is the drain-source voltage at saturation of the P-channel MOS transistor (not shown) within the current source I11.
In such input voltage ranges, a sufficient drain-source voltage is not established across the MOS transistor within the constant current source I12, and therefore the bias current I2 is set nil. As a result, the differential transistor pair DF11 is deactivated.
The current level on the output terminal OUT is correspondingly obtained through the same analysis as the forgoing, and the current level IOUT on the output terminal OUT is represented by the following formula in any case where the differential amplifier circuit operates to draw or supply a current through the output terminal:IOUT=kI2  (17)
The above-described analysis proves that the drive capability of the differential amplifier circuit directly depends on the bias currents fed to the differential transistor pair; increasing the drive capability requires increasing the bias currents. Additionally, the drive current developed on the output terminal is used for charging or discharging the load capacitance connected with the output terminal OUT of the differential amplifier circuit. Therefore, the operation speed of the differential amplifier circuit depends on the bias currents. In other words, enhancing the operation speed of the differential amplifier circuit requires
Next, power consumption of the differential amplifier circuit shown in FIG. 1 is analyzed in the following.
When the input voltage Vin− is higher than the input voltage Vin+, and the difference between the input voltages Vin− and Vin+ are equal to or above the minimum voltage difference ΔVid defined by formula (7), the power source VDD provides the constant current source I11 with the bias current having a current level of I1, and also provides the common terminal of the current mirror circuit CM13 with a current having a current value of 2·I2. Therefore, the total static power consumption P(Tota1) is represented by the following formula, if the current through the output terminal OUT is ignored:P(Total)=VDD(I1+2I2)  (18)
On the other hand, when the input voltage Vin− is lower than the input voltage Vin+, and the difference between the input voltages Vin− and Vin+ is equal to or above the minimum voltage difference ΔVid defined by formula (7), the power source VDD provides the constant current source I11 with the bias current having the current level of I1, the common terminal of the current mirror circuit CM14 with a current having the current level of 2·I2, and the input terminal of the current mirror circuit CM15 with a current having the current level of I1+I2. Therefore, the total static power consumption P(Total) is represented by the following formula, if the current through the output terminal OUT is ignored:P(Total)=VDD(2I1+3I2)  (19)
The conventional differential amplifier shown in FIG. 1 suffers from various drawbacks. Firstly, enhancing the operating speed requires increasing the bias currents developed by the constant current sources I11 and I12.
Additionally, the circuit architecture of the conventional differential amplifier is complicated; for example, two sets of differential transistors pairs DF11 and DF12 within the conventional differential amplifier necessitates performing an increased number of current mirroring steps.
Furthermore, an increased number of the current mirror circuits develop output currents in response to the bias currents distributed by the constant current sources I11 and I12, and this undesirably increases the power consumption.
Additionally, there are different numbers of transistors along a signal path from the differential transistor pair DF11 to the output terminal OUT, and along another signal path from the differential transistor pair DF12 to the output terminal OUT. That is, the signal path from the differential transistor pair DF12 requires additional one current mirroring step by using the current mirror circuits CM13 or CM14 to develop the output current to be added to the output current associated with the differential transistor pair DF11. In other words, the signal path from the differential transistor pair DF12 to the output terminal OUT is long compared to that from the differential transistor pair DF11. This implies that the conventional differential amplifier circuit exhibits different characteristics in the cases where only the differential transistor pair DF11 is activated and where only the differential transistor pair DF12 is activated.